In the field of liquid crystal display (LCD) technology or the field of organic light emitting display (OLED) technology a thin film transistor (TFT) is used as a switch for charging and discharging a pixel unit, and the magnitude of the leakage current thereof is one of the important parameters influencing the performance of a liquid crystal screen.
In the prior art, an amorphous silicon (a-Si) material with good stability and processability has always been used in the active layer of the TFT, however, the carrier mobility of the a-Si material is low and incapable of meeting the requirements of a display device with large dimensions and high resolution, and in particular, incapable of meeting the requirements of the next generation of active matrix organic light emitting device (AMOLED). Compared with an amorphous silicon (a-Si) thin film transistor, a polycrystalline silicon TFT, in particular, a low-temperature polycrystalline silicon TFT, is higher in electron mobility and lower in leakage current, and gradually rep laces the amorphous silicon thin film transistor and becomes the mainstream of thin film transistors already.
In an existing preparation technology of a low-temperature polycrystalline silicon thin film transistor, a source electrode and a drain electrode are formed by doping, that is, the source electrode, the drain electrode and an active layer are located in the same layer.
A common low-temperature polycrystalline silicon TFT is a single-gate TFT, that is, one TFT has one gate electrode, one active layer, one source electrode and one drain electrode, in order to reduce the leakage current of the single-gate TFT, a double-gate TFT structure has been proposed in the prior art, that is, two TFTs are serially connected to form a double-gate TFT, which have two gate electrodes, one source electrode, one drain electrode and two electrically-connected active layers. The leakage current of the double-gate TFT in a turned-off state is 1-2 orders of magnitudes less than that of a single-gate TFT with the same width-length ratio. However, the occupied area of the double-grid TFT on a display substrate is larger than that of the single-grid TFT, which influences the aperture ratio of pixels of a display device, and is adverse to realize a high-resolution (high-PPI) display product.
Specifically, for a liquid crystal display device, one double-gate TFT is provided in each sub-pixel. For an organic light emitting display device, a plurality of single-gate TFTs and/or double-gate TFTs are provided in each pixel, and the single-gate TFTs and/or the double-gate TFTs form a driving circuit used for driving the OLED to emit light. The aperture ratio of pixels is low, and it is difficult to manufacture a high-PPI liquid crystal display device.
The pixels in the liquid crystal display device are taken as an example for description, and FIG. 1 shows a double-gate TFT structure in an pixel in a liquid crystal display device in the prior art. Referring to FIG. 1, the double-gate TFT structure comprises two double-gate TFTs 20 connected to the same gate line 10, and each of the double-gate TFTs is used as a charge-discharge switch for its corresponding pixel. Each of the double-gate TFTs 20 comprises: a first gate electrode 201 and a second gate electrode 202 which are connected with the gate line 10, respectively; and a first active layer 203 and a second active layer 204 which correspond to the first gate electrode 201 and the second gate electrode 202, respectively, wherein the first active layer 203 and the second active layer 204 are electrically connected through a connection layer 205, and the first active layer 203 and the second active layer 204 are distributed in a straight-line shape.
Because the two double-gate TFTs 20 share the gate line 10, regardless of whether the two double-gate TFTs 20 share a data line 30, the double-gate TFTs occupy large areas, thus resulting in low aperture ratio of pixels.
Referring to FIG. 1, when the two double-gate TFTs 20 share the data line 30, because the connection point (point b) where the data line 30 and the two double-gate TFTs 20 are connected exists, the line width at a position (point a) on the gate line 10 adjacent to the point b is reduced, thus resulting in a risk of line breakage of the gate line 10.